1. Field of the Invention
Embodiments of the present invention relates to a display technology field, more particularly, relates to an array substrate, a method for manufacturing the array substrate, a display panel and a method for manufacturing the display panel.
2. Description of the Related Art
Since a low temperature poly-silicon (LTPS) display device has many advantages, such as, high carrier mobility, high resolution, high integration, etc., the LTPS display device becomes a main technology trend in display field. On the same one substrate, the number of color filter units increases as pixel size decreases. That is, the resolution becomes higher as the pixel size becomes smaller. Because the LTPS display device can achieve the high resolution, a display apparatus having the LTPS display device has a very small pixel size. In order to manufacture the display apparatus with the high resolution, it is necessary to reduce the size of black matrix (BM) in the LTPS display device. Accordingly, in the prior art, manufacturing process of a color filter substrate requires high precision, and assembling process of the color filter substrate and an array substrate also requires high precision. In the prior art, even if very small deviation is occurred during manufacturing the color filter substrate or assembling the color filter substrate and the array substrate, it may greatly decrease aperture ratio of pixel, increase power consumption, and deteriorate display quality of the display apparatus.
FIG. 1 is an illustrative local view of a LTPS array substrate in the prior art. A process of manufacturing the LTPS array substrate shown in FIG. 1 mainly comprises steps of: forming a shield metal (SM) layer 5 on a substrate in a zone corresponding to a channel of a thin film transistor; and forming a buffer layer, a polycrystalline silicon layer 1, a gate insulation layer, a gate line 2, a first insulation layer, a data line 3, an organic resin layer, a common electrode layer, a second insulation layer and a pixel electrode in this order on the substrate on which the SM layer 5 is formed. The SM layer 5 is formed to block the channel of the thin film transistor, so as to prevent a light leakage current from being generated. In the prior art, the SM layer 5 of the array substrate can block only the channel of the thin film transistor, and a zone between adjacent color filter units is blocked by the BM. As shown in FIG. 1, a zone on the array substrate corresponding to the color filter unit of the color filter substrate is referred as a first corresponding zone 6, and a zone on the array substrate corresponding to the black matrix of the color filter substrate is referred as a second corresponding zone 7. In order to satisfy the requirement of high aperture ratio of pixel, in the prior art, it is necessary to narrow the width of the black matrix between adjacent color filter units as possible. Thereby, the manufacturing process of the color filter substrate requires high precision, increasing the difficulty of manufacturing the color filter substrate. Furthermore, as the width of the black matrix becomes smaller, assembling process of the color filter substrate and the array substrate requires higher precision, increasing the difficulty of assembling the color filter substrate and the array substrate at the later stage.